Where Can You Find Free JITTER SPEED TEST Resources

 Where Can You Find Free JITTER SPEED TEST Resources

The total integrated jitter of this PLL measured from 10kHz to 100MHz is 1.8ps. Integrating from 10kHz to 10MHz provides a result of 1.6ps, showing that little accuracy is lost by terminating the measurement at 10MHz. The deviation between the measurement and the simulation close to the loop bandwidth integrates to 0.2ps – a very small difference in the end result.

Potential causes for the difference between the measurement and the simulation include power supply noise from the voltage regulator on ourJitter Speed Test PCB, a difference in measurement and simulation temperature.

The accuracy of this correlation has been demonstrated multiple times and the results correlate well with the Periodic Noise results. This gives us great confidence in the results from AFS and provides our customers with assurance that the power, area and performance tradeoffs we have performed to optimize the PLLs we deliver to them will be seen in their products. The runtime of this simulation makes it practical as a sign-off simulation when the jitter is critical.

Traditional SPICE simulators do not offer feasible Transient Noise capabilities so we cannot compare simulation runtime with SPICE.

For many system designers the time the PLL takes to lock from startup is important. With its 108,000 extracted circuit elements this PLL, a regular Transient simulation, is very challenging for SPICE. The node voltage accuracy mentioned above is important as small errors can accumulate resulting in wildly inaccurate predictions of locking time.

Figure 5 shows the loop filter voltage of this PLL in two operating modes as the PLL moves from power on to locking. In integer mode (with the Δ Σ Modulator turned off) the lock time simulated by AFS is 15.6µs, very close to the measured 15.8µs. The predicted lock time in Fractional mode is similarly accurate.

With traditional SPICE this simulation takes roughly three weeks. With AFS we completed this simulation in 30 hrs, a speedup of 18×. Consequently we are able to include LOCK simulations as a sign-off item prior to delivering a new PLL. When purchasing a new, or customized PLL, our customers appreciate not being asked to choose between later delivery and risk.

Berkeley Design Automation assures its customers that they will see a speedup of at least 5× when comparing AFS to their SPICE simulator on a single core. Compared to the simulators we have tried AFS does better than this, even for small simulations. For example, a transient simulation of the extracted circuit of the VCO in SPICE took 14 min while AFS took 1.5 min, a speedup of over 9×.

Conclusions

The AFS Platform from Berkeley Design Automation has become an essential tool at Silicon Creations.

We see excellent correlation between simulation predictions and silicon measurements within 0 – 3 dB for Transient Phase Noise and accurate predictions of PLL LOCK times.

These transient simulation results are available with runtimes up to 18× faster than before, making them feasible for use as sign-off for delivery of new PLLs.

The predicted jitter correlates well with our Matlab models and silicon, increasing our customers’ confidence in our models and our designs.

Acknowledgements

The author thanks David Lee and Mick Tegethoff, Berkeley Design Automation for their contributions and TSMC for their reliable process models.